1. Field of the Invention
The present invention relates to an information processing system and method therefor. More specifically, the invention relates to an information processing system and method for high speed processing of instructions.
2. Description of the Related Art
In a conventional information processing system operative under von Neumann system, when an instruction for accessing a memory is processed during sequential execution of instruction string, it takes a control architecture not to advance the process operation in an arithmetic portion to the next instruction until memory access is completed and to place the system in a waiting state during a memory access cycle of the corresponding instruction.
Particularly, in the case where the memory access is performed in execution of an instruction for a data reading operation (loading operation), it is inherent to place arithmetic process into waiting state since the loaded data is used in execution of instructions subsequent to the load instruction of data read out from the memory.
Progress of instruction processing in the conventional von Neumann type processor will be briefly discussed hereinafter with reference to FIG. 19. In an instruction string A of FIG. 19, partial instruction strings A1, A2, A3, an arithmetic logic operation instruction (hereinafter referred to as ALU operation instruction) A4 and a partial instruction string A5 are executed in series. In order to execute the ALU operation instruction, two data loading, i.e. load AL1 after partial instruction string A1 and load AL2 after partial instruction string A2 are necessary. In FIG. 19, the portions indicated by curved arrows represent the period from initiation to completion of data loading. Similarly in case of an instruction string B, partial instruction strings B1, B2, B3, ALU operation instruction B4 and a partial instruction string B5 are executed in series. Also, for execution of the ALU operation instruction B4, data loading of two data, i.e. loads BL1 and BL2 is required.
In the conventional von Neumann type processor, when such instruction string is to be executed, the process cannot be advanced to the instruction string A2 subsequent to completion of the instruction string A1 unless data loading of the load AL1 to be used in the ALU operation instruction A4 is completed. During this period, the arithmetic unit is held inoperative and maintained in the waiting state for completion of the loading process. Therefore, the process of instruction string is progressed in the sequence of FIG. 19.
As shown in FIG. 19, in the typical conventional von neumann type information processing system, it is not possible to perform parallel execution at the instruction level. Accordingly, in the conventional system, when a period from initiation of memory access to completion is long relative to a period for executing one instruction of the information processing system, there is inherently arisen a period wasted without performing the arithmetic operation in the information processing system to degrade throughput of the information processing system.